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14-megapixel cmos image senso r IBIS4-14000-M ibis4-14000-c cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05709 rev. *a revised february 27, 2006 features the ibis4-14000 is a cmos acti ve pixel image sensor that is comprised of 14 megapixels with 3048 x 4560 active pixels on an 8m pitch. the sensor has a focal plane array of 36 x 24mm 2 and operates in rolling shutter mode. at 15 mhz, 3 fps are achieved at full resolution. on-chip fpn correction is available the pixel design is based on the high-fill-factor active pixel sensor technology of cypres s semiconductor corporation (us patent no. 6,225,670 and other s). the sensor is available in a monochrome version and a bayer (rgb) patterned color filter array. this data sheet allows the user to develop a camera system based on the described timing and interfacing. applications ? digital photography ? document scanning ? biometrics table 1. key performance parameters parameter typical value active pixels 3048 (h) x 4560 (v) pixel size 8 m x 8 m optical format 35 mm shutter type rolling shutter master clock 15 mhz frame rate 3 fps at full resolution sensitivity (@ 650 nm) 1256 v.m 2 /w.s full well charge 65.000 e- ktc noise 35 e- dark current 223 e-/s dynamic range 65.4 db supply voltage 3.3v power consumption < 176 mw color filter array mono and rgb packaging 49-pins pga
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 2 of 30 table of contents 1.0 specifications .... ................ ................ ................ ................. ................ ............. .......... ................................ 4 1.1 general specifications .................................................................................................... ............................................... 4 1.2 electro-optical specifications .................... ........................................................................ ............................................. 4 1.2.1 overview ................................................................................................................ ............................................. 4 1.2.2 spectral response curve ... .............................................................................................. .................................. 5 1.2.3 electro-voltaic response curv e .......................................................................................... ................................ 5 1.3 electrical specifications ................................................................................................. ................................................ 6 1.3.1 absolute maximum ratings . ............................................................................................... ................................. 6 1.3.2 recommended operating specific ations .................................................................................... ........................ 6 1.3.3 bias currents and references ............. .............. .............. .............. .............. .............. ......... ................................ 6 2.0 architecture and operation ................................................................................................ ............... 7 2.1 floor plan ................................................................................................................ ...................................................... 7 2.2 pixel specifications ...................................................................................................... .................................................. 8 2.2.1 architecture ............................................................................................................ ............................................. 8 2.2.2 fpn and prnu ............................................................................................................ ....................................... 9 2.2.3 color filter array (cfa) ................................................................................................ ....................................... 9 2.2.4 output stage ............................................................................................................ ........................................... 9 2.2.5 output amplifier crossbar switch (multiplexer) .......................................................................... ....................... 10 2.3 readout and subsampling modes ... .............. .............. .............. .............. .............. ........... ......... ................................. 11 2.4 sensor readout timing diagrams ............ .............. .............. .............. .............. .............. .......... ................................... 14 2.4.1 row sequencer ........................................................................................................... ...................................... 14 2.4.2 timing pulse pattern for readout of a pixel . ............................................................................ ......................... 16 2.4.3 fast frame reset timing diagram ........................................................................................ .......................... 16 2.5 spi register ............................................................................................................. .................................................. 18 2.5.1 spi interface architecture .............................................................................................. ................................... 18 2.5.2 spi register definition ................................................................................................. ..................................... 18 3.0 pin configuration ......................................................................................................... .......................... 20 4.0 geometry & mechanical .................................................................................................... .................. 22 4.1 die geometry .............................................................................................................. ................................................ 22 4.2 pin number assignment ..................................................................................................... ......................................... 23 4.3 package drawings ......................................................................................................... ............................................. 24 4.4 die placement dimensions and accuracy .............. ....................................................................... .............................. 25 4.5 cover glass ............................................................................................................... .................................................. 26 4.5.1 IBIS4-14000-M (monochrome) .............................................................................................. ............................ 26 4.5.2 ibis4-14000-c (color) ................................................................................................... .................................... 26 5.0 storage and handling ...................................................................................................... .................... 27 5.1 storage conditions ........................................................................................................ .............................................. 27 5.2 handling precautions ..................................... ................................................................. ............................................ 27 5.3 esd ....................................................................................................................... ...................................................... 27 5.4 dust and contamination .................................................................................................... .......................................... 27 5.5 soldering ................................................................................................................. .................................................... 27 5.6 precautions and cleaning .................................................................................................. ......................................... 27 5.7 rohs (lead-free) compliance ......................... ...................................................................... ....................................... 27 6.0 ordering information ...................................................................................................... .................... 29 6.1 part numbers .............................................................................................................. ................................................ 29 6.2 evaluation kit ............................................................................................................ ................................................... 29
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 3 of 30 list of figures figure 1. ibis4-14000 spectral response curve .................................................................................. .................. 5 figure 2. ibis4-14000 electro-volt aic response curve....................... .................................................... ................ 5 figure 3. block diagram of the ibis4-14000 image sensor ........................................................................ ............ 7 figure 4. location of the 24 additio nal columns and rows, scan direction of the array ....................................... 8 figure 5. pixel and column stru cture schematic ................................................................................. ................... 8 figure 6. color filter arrangem ent on the pixels ............................................................................... ...................... 9 figure 7. color filter response curve .......................................................................................... .......................... 9 figure 8. output amplifier cros sbar switch ..................................................................................... ...................... 10 figure 9. b and c subsample mode ............................................................................................... ....................... 12 figure 10. d and e subsample mode ..................... ......................................................................... ...................... 13 figure 11. f subsample mode.................................................................................................... ........................... 14 figure 12. line readout timing................................................................................................. ............................ 15 figure 13. row readout timing sequence ......................................................................................... .................. 16 figure 14. fast reset sequence timing .......................................................................................... ..................... 17 figure 15. spi interface ................................ ....................................................................... .................................. 18 figure 16. die geometry and location of pixel (0,0 ) ............................................................................ ................. 22 figure 17. pin number assignment ............................................................................................... ........................ 23 figure 18. package dimensions .......................... ........................................................................ .......................... 24 figure 19. die placement ...... ................................................................................................. ............................... 25 figure 20. tolerances .......................................................................................................... .................................. 25 figure 21. d-263 transmittance curve........................................................................................... ....................... 26 figure 22. s8612 transmittance curve (w/o ar coat ing).......................................................................... ............ 26 list of tables table 1. key performance parameters ........................................................................................... ........................ 1 table 2. ibis4-14000 general specifications ..... .............................................................................. ...................... 4 table 3. ibis4-14000 electro-optical specifications ........................................................................... .................... 4 table 4. ibis4-14000 absolute ma ximum ratings ................................................................................. ................ 6 table 5. ibis4-14000 recommended op erating specifications ..................................................................... ........ 6 table 6. ibis4-14000 bias currents ............................................................................................. ........................... 6 table 7. subsampling modes .................................................................................................... ........................... 11 table 8. frame rates and resolution for various subsample modes ............................................................... .. 11 table 9. timing constraints for the row sequencer ............................................................................. ............... 15 table 10. fast reset timing cons traints ....................................................................................... ....................... 17 table 11. timing requirements se rial-parallel interface ....................................................................... ............... 18 table 12. serial sensor parameters register bit de finitions ................................................................... ............. 19 table 13. pin list ............................................................................................................ ...................................... 20 table 14. chemical substances and in formation about any intent ional content ................................................. 27 table 15. ordering inform ation ................................................................................................ ............................. 29
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 4 of 30 1.0 specifications 1.1 general specifications 1.2 electro-optical specifications 1.2.1 overview all parameters are measured us ing the default settings (see recommended operating conditions) unless otherwise specified. note: 1. settings: vdd = 3.3v, vddr = 4v and vdd_array = 3v. table 2. ibis4-1400 0 general specifications parameter value remarks pixel architecture 3t pixel te c h n o l o g y cmos pixel size 8 x 8 m 2 resolution 3048 x 4560 13.9 megapixels power supply 3.3v shutter type electronic rolling shutter pixel rate 15 mhz nominal 20 mhz with extra power dissipation. frame rate 3.25 frames/s full resolution with 4 parallel analog outputs @ 15 mhz/channel power dissipation 176 mw 53 ma table 3. ibis4-14000 elec tro-optical specifications parameter value remarks effective conversion gain 18.5 v/e- 25 v/e- full range. see note 1. linear range. see note 1. spectral response * fill factor 0.22 a/w (peak) peak q.e. * fill factor 45% between 500 and 700 nm. full well charge 65000 electrons see note 1. linear range 90% of full well charge linearity definition: < 3% deviation from straight line through zero point. temporal noise (ktc noise limited) 35 electrons ktc noise, being the dominant noise source in the dark at short integration times. dynamic range 1857:1 (65.4 db) see note 1. linear dynamic range 1671:1 (64.5 db) see note 1. 3% deviation. average dark current 55 pa/cm 2 average value @ 24c lab temperature. dark current signal 223 electrons/s 4.13 mv/s average value @ 24c lab temperature. mtf at nyquist 0.55 in x 0.57 in y measured at 600 nm. fixed pattern noise (local) 0.11% vsat rms average value of rms variation on local 32 x 32 pixel windows. fixed pattern noise (global) 0.15% vsat rms prnu <1% rms of signal anti-blooming 10 5 charge spill-over to neighboring pixels (= ccd blooming mechanism)
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 5 of 30 1.2.2 spectral response curve 1.2.3 electro-voltaic response curve figure 1. ibis4-14000 spectral response curve figure 2. ibis4-14000 electro-voltaic response curve
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 6 of 30 1.3 electrical specifications 1.3.1 absolute maximum ratings 1.3.2 recommended oper ating specifications 1.3.3 bias currents and references note: 2. tolerance on bias reference voltages: 150 mv due to process variances. table 4. ibis4-14000 absolute maximum ratings parameter description value unit v dc dc supply voltage ?0.5 to +4.5 v v in dc input voltage ?0.5 to v dc + 0.5 v v out dc output voltage ?0.5 to v dc + 0.5 v i dc current per pin; any single input or output 50 ma t stg storage temperature range ?10 to 66 (@ 15% rh) ?10 to +38 (@ 86% rh) (rh = relative humidity) c altitude 8000 feet table 5. ibis4-14000 recomme nded operating specifications parameter description min. typ. max. unit vdd nominal power supply 3.3 3.6 v vddrl vddrr reset power supply level 4 v vdd_array pixel supply level 3 v darkref dark reference offset level 1.7 2.65 3 v gndab anti-blooming ground level 0 0 1 v v out analog output level 0.5 3 v v ih logic input high level 2.5 3.3 v v il logic input low level 0 1 v t a commercial operating temperature 0 50 c (@ 15% rh) t a commercial operating temperature 0 38 c (@ 86% rh) table 6. ibis4-14000 bias currents [2] pin number pin name connection input current pin voltage 1 obias 10k to vdd 179 a 1.51v 36 cbias 22k to vdd 91 a 1.29v 37 pcbias 22k to vdd 91 a 1.29v 48 xbias 10k to vdd 181 a 1.49v 49 abias or 10m to vdd 0.8v
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 7 of 30 2.0 architecture and operation 2.1 floor plan the basic architecture of the sensor is shown in figure 3 . the y shift registers point at a row of the imager array. this row is selected and/or reset by the row drivers. there are 2 y shift registers: one points at the row that is read out and the second one points at the row to be reset. the second pointer may lead the first pointer by a specific number of rows. in that case, the time difference between both pointers is the integration time. alternatively, both shift registers can point at the same row for reset and readout for a faster reset sequence. when the row is read out , it is also reset in order to do double sampling for fixed pattern noise reduction. the pixel array of the ibis4-14000 consists of 4536 x 3024 active pixels and 24 additional columns and rows, which can also be addressed (see figure 4 ). the column amplifiers read out the pixel information and perform the double sampling operation. they also multiplex the signals on the readout buses, which are buffered by the output amplifiers. the shift registers can be configured for various subsampling modes. the output amplifiers can be individually powered down. and some other extra f unctions are foreseen. these options are configurable via a serial input port. pixel array 4560 x 3048 active pixels x-shift register y shift register 3048 column amplifiers 4560 row drivers y shift register 4560 row drivers clk_yr sync_yr 4 parallel analog outputs pixel (0,0) shs shr clk_x sync_x clk_yl sync_yl reset syr syl figure 3. block diagram of the ibis4-14000 image sensor
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 8 of 30 2.2 pixel specifications 2.2.1 architecture 3024 x 4536 active pixels 24 x 4536 dummy pixels ------------- sky -------------- 3024 x 24 dummy pixels 4 analog outputs top of camera 3048 x 4560 total pixels p ixel 0,0 figure 4. location of the 24 additional columns and rows, scan direction of the array figure 5. pixel and colu mn structure schematic reset vdd_array select column pc shs shr m1 m2 m3
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 9 of 30 the pixel is a classic 3-transistor active pixel. the photodiode is a high-fill-factor n-well/p-su bstrate diode. separate power supplies are foreseen: general power supply for the analog image core (vdd), power supply for the reset line drivers (vddr) and a separate power supply for the pixel itself (vddarray). 2.2.2 fpn and prnu fixed pattern noise correction is done on chip with the so-called double sampling technique. the pixel is readout and this voltage value is sampled on capacitor shs. after read out the pixel is reset again and this value is sampled by shr. both sample and reset values of each pixel are subtracted in the column amplifiers to subt ract fpn. raw images taken by the sensor typically feature a residual (local) fpn of 0.11% rms of the saturation voltage. the photo response non uniformity (prnu), caused by mismatch of photodiode node capacitances, is not corrected on-chip. measurements indicate that the typical prnu is <1% rms of the signal level. 2.2.3 color filter array (cfa) the ibis4-14000 can also be processed with a bayer rgb color pattern. pixel (0,0) has a green filter and is situated on a green-red row. figure 7 shows the response of the color filter array as function of the wavelength. note that this response curve includes the optical cross talk a nd the nir filter of the color glass lid as well (see section 4.5 for response of the color glass lid). 2.2.4 output stage unity gain buffers are implemented as output amplifiers. these amplifiers can be directly dc-coupled to the analog-digital converter or coupled to an external program- mable gain amplifier. the (dark reference) offset of the output signal is adjustable between 1.7v and 3v. the amp lifier output signal is negative going with increasing light le vels, with a max. amplitude of 1.2v (at 4v reset voltage, in hard reset mode). the output signal range of the output ampl ifiers is between 0.5v and 3v. figure 6. color filter arrangement on the pixels figure 7. color filter response curve
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 10 of 30 notes on analog video signal and output amplifier specifica- tions: ? video polarity: the video signal is negative going with increasing light level. ? signal offset: the analog offset of the video signal is settable by an external dc bias (pin 12 darkref). the settable range is between 1.7v and 3v, with 2.65v being the nominal expected set point. the output range (including 1.2v video signal) is thus between 3v and 0.5v. ? power control: the output amplifiers can be switched between an ?operating? mode an d a ?standby? mode via the serial port of the imager (see spi register configuration). ? coupling: the ibis4-14000 can be dc- or ac-coupled to the ad converter. 2.2.5 output amplifier crossbar switch (multiplexer) a crossbar switch is availabl e that routes the green pixels always to the same output (this is useful for a color device to avoid gain and offset differences between green pixels). the switch can be controlled automa tically (with a toggle on every clk_y rising edge) or manually (through the spi register). figure 8 shows how it works. a pul se on sync_y resets the crossbar switch. the initial stat e after reset of the switchboard is read from the spi contro l register. when the automatic toggling of the switchboard is enabled, it toggles on every rising edge of the clk_y clock. separate pins are used for the sync_y and clk_y signals on the crossbar logic these pins can be connected to the sync_yl and clk_yl pins of the shift register that is used for readout. . power power power power q sync_yr clk_yr manual figure 8. output amplifier crossbar switch
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 11 of 30 2.3 readout and subsampling modes the subsampling modes available on the ibis4-14000 are summarized in table 7 . each mode is selected independently for the x and y shift registers. the subsampling mode is configured via the serial input port of the chip. the y and x shift registers have some different subsampling modes, due to constraints in the design of the chip. the baseline full resolution operation mode uses 4 outputs to read out the entire image. 4 cons ecutive pixels of a row are put in parallel on the 4 parallel outputs. subsampling is implemented by a shift register with hard-coded subsample modes. depending on the selected mode, the shift register skips the required number of pixels when shifting the row or column pointer. the x shift register always selects 4 consecutive columns in parallel. subsampling in x can be done by activating one of the modes wherein a multiple of 4 consecutive columns is skipped on a clk_x pulse. the y shift register selects a single row. it will consecutively select 2 adjacent rows and then skip an amount of rows set by the subsample mode. this imple- mentation is chosen for easy subsampling of color images through a 2-channel readout. in this way color data from 2x2 pixels is made available in all subsample modes. on monochrome sensors this is not required?only one output can be used and the each second row selected by the y shift register can be skipped. this doubles the frame rate. note that for 2 or 1 channel readout, the not-used output amplifiers can be powered down through the spi shift register. rows can also be skipped by extra clk_y pulses. it is not required to apply additional control pulses to rows that are skipped. this is a way to implement extra subsampling schemes. for example, to support the 24:1 x shift register mode also vertically, the y shift register can be set to the 12:1 mode and an additional clk_y pulse needs to be given at the start of each row. table 8 lists the frame rates of the ibis4-14000 in various subsample modes with only one output. the row blanking time (dead time between readout of successive rows) has been set to 17.5 s. note that the 24 additional columns and rows (see figure 4 ) do not subsample. table 7. subsampling modes subsampling modes programmed into spi register x shift register subsampling settings bitcode mode use 000 001 010 1:1 full resolution (all columns) full resolution (4 outputs) 4:1 subsampling 011 24:1 select 4 columns/ skip 20 24:1 subsampling ( 2 outputs) 100 8:1 select 4 columns / skip 4s 8:1 subsampling (2 outputs) 101 12:1 select 4 columns / skip 8 12:1 subsampling (2 outputs) y shift register subsampling settings bitcode mode use 000 010 100 4:1 select 2 rows / skip 2 4:1 subsampling 001 1:1 full resolution (all rows) full resolution 011 6:1 select 2 rows / skip 4 6:1 subsampling 101 12:1 select 2 rows / skip 10 12:1 subsampling table 8. frame rates and resolution for various subsample modes ratio # outputs image resolution frame rate [frames/s] frame readout time [s] 1:1 4 3024 x 4536 3.25 0.308 4:1 1 756 x 1134 12.99 0.077 8:1 1 378 x 567 41.30 0.024 12:1 1 252 x 378 77.13 0.013
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 12 of 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 123456789101112131415161718192021222324 mode b - 1:1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 123456789101112131415161718192021222324 mode c - 1:4 figure 9. b and c subsample mode
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 13 of 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 123456789101112131415161718192021222324 mode d - 1:6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 123456789101112131415161718192021222324 mode e - 1:8 figure 10. d and e subsample mode
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 14 of 30 2.4 sensor readout timing diagrams 2.4.1 row sequencer the row sequencer controls pulses to be given at the start of each new line. figure 12 shows the timing diagram for this sequence. the signals to be controlled at each row are: ? clk_yl and clk_yr: these are the clocks of the yl and yr shift register. they can be driven by the same signals and at a continuous frequency. at every rising edge, a new row is being selected. ? select: this signal connects the pixels of the currently sampled line with the columns. it is important that pc and select are never active together. ? pc: an initialization pulse that needs to be given to precharge the column. ? shs (sample & hold pixel signal): this signal controls the track & hold circuits in the column amplifiers. it is used to sample the pixel signal in the co lumns. (0 = track ; 1 = hold) ? reset: this pulse resets the pixels of the row that is currently being selected. in rolling shutter mode, the reset signal is pulsed a second time to reset the row selected by the yr shift register. for ?reset black? dark reference signals, the reset pulse can be pulsed also during the first pc pulse. normally, the rising edge of reset and the falling edge of pc occur at the same position. the falling edge of reset lags behind th e rising pc edge. ? shr (sample & hold pixel reset level): this signal controls another track & hold circuit in the column amplifiers. it is used to sample the pixel rese t level in the columns (for double sampling). (0 = track ; 1 = hold) ? syl (select yl register): selects the yl shift register to drive the reset line of the pixel array ? syr (select yr register): sele cts the yr shift register to drive the reset line of the pixel array. for rolling shutter appli- cations, syl and syr are complementary. in full frame readout, both registers may be selected together, only if it is guaranteed that both shift regi sters point to the same row. this can reduce the row blanking time. ? sync_yr and sync_yl: synchronization pulse for the yr and yl shift registers. the sync_yr/sync_yl signal is clocked in during a rising edge on clk_yr/clk_yl and resets the yr/yl shift register to the first row. both pulses are pulsed only once each fr ame. the exact pulsing scheme depends on the mode of use (full frame/ rolling shutter). a 200 ns set-up time applies. see table 9 . ? sync_x: resets the column poi nter to the first row. this has to be done before the end of the first pc pulse, in case when the previous line has not been read out completely. figure 12 shows the basic timing diagram of the ibis4-14000 image sensor and ta ble 9 shows the timing specifications of the clocking scheme 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9101112131415161718192021222324 mode f - 1:1 2 figure 11. f subsample mode
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 15 of 30 notes: clk = one clock period of the master clock, shortest system time period available. in the above timing diagram, the yr shift register is used for the electronic shutter. the clk_yr is driven identically as clk_yl. the sync_yr pulse leads the sync_yl pulse by a given number of rows. relative to the row timing, both sync pulses are given at the same time position. sync_yr and sync_yl are only pulsed once each frame, sync_yl is pulsed when the first row will be read out and figure 12. line readout timing clock_yl pc shs select reset shr syl syr sync_yr sync_yl a bb c d e f c e d f g h h i jj once each frame for each new row only when the electronic shutter is used h optional reset pulse for reset black k l m table 9. timing constraints for the row sequencer symbol min. typ. description a 200 ns 600 ns min. sync set-up times. sync_y is clocked in on rising edge on clk_y. sync_y pulse must overlap clk_y by one clock period. se t-up times of 200 ns apply after sync edges. within this set-up time no rising clk edge may occur b 2.7 s duration of pc pulse c 10 s delay between falling edge on pc and ri sing edge on shs/shr. duration of shs/shr pulse d 1.3 s delay between rising edge on pc and rising edge on select e 6.5 s delay between rising edge on select and rising edge on shs/shr. f 100 ns delay between rising edge on shs and falling edge on select. g 1.4 s delay between falling edge of select and rising edge of reset h 5 s duration of reset pulse i 1.28 s delay between rising edge on shr and rising edge on syr j h+2*clk 500 ns syl and syr pulses must over lap second reset pulse at both sides by one clock cycle k 240 ns duration of clock_y pulse l 3 s delay between falling edge of clk_y and falling edge of pc and shs m 500ns delay between falling edge of reset and falling edge of pc and shr
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 16 of 30 sync_yr is pulsed for the electronic shutter at the appro- priate moment. this timing assumes that th e registers that control the subsampling modes have been loaded in advance (through the spi interface), before the pulse on sync_yl or sync_yr. the second reset pulse and the pulses on syl and syr (all pulses drawn in red) are only applied when the rolling electronic shutter is used. for full frame integration, these pulses are skipped. the sync_y pulse is also used to initialize the switchboard (output multiplexer). this is also done by a synchronous reset on the rising edge of clk_y. normally the switchboard is controlled by the shift register used for readout (this is the yl shift register). this means that pin sync_y can be connected to sync_yl, and pin clk_y can be connected to clk_yl. the additional reset black pulse (indicated in dashed lines in figure 12 ) can be given to make one or more lines black. this can be useful to generate a dark reference signal. 2.4.2 timing pulse pattern for readout of a pixel figure 13 shows the timing diagram to preset (sync) the x shift register, read out the image row, and analog-digital conversion. there are 3 tasks: ? preset the x shift register: apply a low level to sync_x during a rising edge on clk_x at the start of a new row ? readout of the imag e row: pulse clk_x ? analog-digital conversion: clock the adc the sync pulses perform a synchronous reset of the shift registers to the first row/column on a rising edge on clk. this is identical for all shift registers (yr, yl and x). ? important the sync_x signal has a set-up time ts of 150 ns. for the yr and ys shift registers, the set-up time is 200 ns. clk_x must be stable at least during this set-up time. in the case where a partial row readout has been performed, 2 clk_x pulses (with sync_x = low) are required to fully deselect the column where t he x pointer has been stopped. a single clk_x will leave the column partially selected, which will then have a different response when read out in the next row. when full row readout has been performed, the last column will be fully deselected by a single clk_x pulse (with sync_x = low). the x-register is reset by a single clk_x pulse (with sync_x = low). in case of partial row readout, the sync_x pulse has to be given before the sample pulses (shr and shs) of the row sampling process, in order to avoid a different response of the last column of the previous window. for the x shift register, the analog signal is delayed by 2 clock periods before it becomes available at the output (due to internal processing of the signal in the columns and output amplifier). the figure gives an example of an adc clock for an adc that samples on the rising edge. 2.4.3 fast frame reset timing diagram figure 14 shows the reset timing for a fast frame reset. syl and syr can be kept both high to make the reset mechanism faster and reduce propagation delays. pc, shs, shr can be kept high since they don?t interact with the pixel reset mechanism. table 10 lists timing specifications for reset, clk_y and select. sync_x clk_x clk_adc (exam ple) a nalog output pixel 1 pixel 2 pixel 3 x ts ts figure 13. row readout timing sequence
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 17 of 30 table 10. fast reset timing constraints symbol typical description a 0 s delay between rising clk_y edge and reset. b 4 s reset pulse width. c 0 reset hold time. d 1.6 s select pulse width. e 1 s setup hold time. constraint: a + e > 1 us due to propagation delay on pixel select line. clk_y r clk_y l sync_y r sync_y l sh s rese t sh r sy l sy r p c b b a c selec t d e figure 14. fast reset sequence timing
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 18 of 30 2.5 spi register 2.5.1 spi interface architecture the elementary unit cell of the serial to parallel interface consists of two d-flip-flops. the architecture is shown in figure 15 . 16 of these cells are connected in parallel, having a common /cs and sclk form the entire uploadable parameter block, where d in is connected to d out of the next cell. the uploaded settings are applied to the sensor on the rising edge of signal /cs. 2.5.2 spi register definition sensor parameters can be serially uploaded inside the sensor at the start of a frame. the parameters are: ? subsampling modes for x and y shift registers (3-bit code for 6 subsampling modes) ? power control of the output amplifiers, column amps and pixel array. each amplifier can be individually powered up/down ? output crossbar switch control bits. the crossbar switch is used to route the green pixels to the same output amplifiers at all time. a first bit controls the crossbar. when a second bit is set, the first bit will toggle on every clk_y edge in order to automatically route the green pixels of the bayer filter pattern. the code is uploaded serially as a 16-bit word (lsb uploaded first). table 12 lists the register definition. the default code for a full resolution readout is 33342 (decimal) or 1000 0010 0011 1110. d q c d q c din to sensor core dout sclk cs 16 outputs to sensor core sclk din dout unity cell entire uploadable parameter block cs d0 d1 d2 d15 cs sclk din ts data valid tsclk th figure 15. spi interface table 11. timing requiremen ts serial-parallel interface parameter value tsclk 100 ns ts 50 ns th 50 ns
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 19 of 30 3 pins are used for the serial data interface. this interface converts the serial data into an (internal) parallel data bus (serial-parallel interface or spi). the control lines are: ? data: the data input. ls b is clocked in first. ? clk: clock, on each rising edge, the value of data is clocked in ? cs: chip select, a rising edge on cs loads the parallelized data into the on-chip register. the initial state of the register is undefined. however, no state exists that destroys the device. table 12. serial sensor parameters register bit definitions bit description? 0 (lsb) set to zero (0) 1 1 = power on sensor array ; 0 = power-down 2 1 = power up output amplifier 4; 0 = power-down 3 1 = power up output amplifier 3; 0 = power-down 4 1 = power up output amplifier 2; 0 = power-down 5 1 = power up output amplifier 1; 0 = power-down 6 3-bit code for subsampling mode of x shift register: 000 = full resolution 011 = select 4, skip 20 001 = full resolution 100 = select 4, skip 4 010 = full resolution 101 = select 4, skip 8 7 8 9 3-bit code for subsampling mode of y shift registers: 000 = select 2, skip 2 011 = select 2, skip 4 001 = full resolution 100 = select 2, skip 2 010 = select 2, skip 2 101 = select 2, skip 2 10 11 12 crossbar switch (output multiplexer) control bit initial value. this initial value is clocked into the crossbar switch at a sync_yr rising edge pulse (when the array pointers jump back to row 1). the crossbar switch control bit selects the corre spondence between multiplexer busses and output ampli- fiers. bus-to-output correspondence is according to the following table: bus when bit set to 0 when bit set to 1 1 output 1 output 2 2 output 2 output 1 3 (4 outputs) output 3 output 4 4 (4 outputs) output 4 output 3 13 1 = toggle crossbar switch control bit on every odd/eve n line. in order to let green pixels always use the same output amplifier automatically, this bit must be set to 1. on every clk_y rising edge (when a new row is selected), the crossbar switch control bit will toggle. initial value (after sync_y) is set by bit 12. 14 not used. 15 (msb) 1 = power-up sensor array; 0 = power-down
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 20 of 30 3.0 pin configuration table 12 lists the pin configuration of the ibis4-14000. figure 17 shows the assignment of pin numbers on the package. table 13. pin list pin # name function comment 1 obias bias current output amplifiers. connect with 10k ? to vdd and decouple with 100 nf to gnd. 2 gnd ground for output 3. 3 out3 output 3. 4 gnd ground for output 4. 5 out4 output 4. 6 vdd power supply. nominal 3.3v 7 gnd ground. 0v 8 out2 output 2. 9 gnd ground for output 2. 10 out1 output 1. 11 gnd ground for output 1. 12 darkref offset level of output signal. typ. 2.6v. min. 1.7v max. 3v 13 temp1 temperature sensor. located near the output amplifiers (pixel 4536, 0) near the stitch line). any voltage above gnd forward biases the diode. connect to gnd if not used. 14 phdiode photodiode output. yields the equivalent photocurrent of 250 x 50 pixels. diode is located right under the pad. reverse biased by any voltage above gnd connect to gnd if not used. 15 clk_y y clock for switchboard. clocks on rising edge connect to clk_yl (or drive identically) 16 sync_y y sync pulse for switchboard. low active: synchronous sync on rising edge of clk_y connect to sync_yl (or drive identically) 17 temp2 temperature sensor. located near pixel (24,0). any voltage above gnd forward biases the diode. connect to gnd if not used. 18 gndab anti-blooming reference level (= pin 33). typ. 0v. set to 1.5v for improved anti-blooming. 19 gnd ground. 0v 20 vdd power supply. nominal 3.3v 21 vddr power supply for reset line drivers nominal 4v connected on-chip to pin 30 22 clk_yr clock of yr shift register. shifts on rising edge. 23 syr activate yr shift register for driving of reset and select line of pixel array. high active. exact pulsing pattern see timing diagram. both syr = 1 and syl = 1 is not allowed, except when the same row is selected! 24 sync_yr sets the yr shift register to row 1. low active. synchronous sync on rising edge of clk_yr 200 ns set-up time 25 vddarray pixel array power supply (= pin 26). 3v 26 vddarray pixel array power supply (= pin 25). 3v 27 sync_yl sets the yl shift register to row 1. low active. synchronous sync on rising edge of clk_yl 200 ns set-up time. 28 syl activate yl shift regist er for driving of reset and select line of pixel array. high active. exact pulsing pattern see timing diagram. both syr = 1 and syl = 1 is not allowed, except when the same row is selected! 29 clk_yl clock of yl sh ift register. shifts on rising edge.
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 21 of 30 30 vddr power supply for reset line drivers. nominal 4v. connected on-chip to pin 21. 31 vdd power supply. nominal 3.3v 32 gnd ground. 0v 33 gndab anti-blooming reference level (= pin 33). typ. 0v. set to 1v for improved anti-blooming. 34 select control select line of pixel array. high active. see timing diagrams. 35 reset reset of the selected row of pixels. high active. see timing diagrams. 36 cbias bias current column amplifiers. connect with 22 k ? to vdd and decouple with 100 nf to gnd. 37 pcbias bias current. connect with 22 k ? to vdd and decouple with 100 nf to gnd. 38 din serial data input. 16-bit word. lsb first. 39 sclk spi interface clock. shifts on rising edge. 40 cs chip select. data copied to registers on rising edge. 41 pc row initialization pulse. see timing diagrams. 42 sync_x sets the x shift register to row 1. low active. synchronous sync on rising edge of clk_x 150 ns set-up time. 43 gnd ground. 0v 44 vdd power supply. nominal 3.3v 45 clk_x clock of yr shift register. shifts on rising edge. 46 shr row track & hold reset level (1 = hold; 0 = track). see timing diagram. 47 shs row track & hold signal level (1 = hold; 0 = track). see timing diagram. 48 xbias bias current x multiplexer. connect with 10 k ? to vdd and decouple with 100 nf to gnd. 49 abias bias current pixel array. connect with 10 m ? to vdd and decouple with 100 nf to gnd. table 13. pin list (continued) pin # name function comment
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 22 of 30 4.0 geometry & mechanical 4.1 die geometry ground pad, also connected to package ground plane analog output pad ground for output pad (not connected to package ground plane) locations of temperature sensing diodes location of photodiode array 4 output channels pixel 0,0 500 m pin 1 figure 16. die geometry and location of pixel (0,0)
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 23 of 30 4.2 pin number assignment note : ?solid? drawn pins are connected to die attach area for a proper ground plane package back side 1 2 3 4 5 6 13 12 11 10 9 8 7 19 18 17 16 15 14 20 21 22 23 24 25 31 30 29 28 27 26 32 33 34 35 36 37 38 39 40 41 42 43 49 48 47 46 45 44 figure 17. pin number assignment
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 24 of 30 4.3 package drawings all dimensions in mm figure 18. package dimensions
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 25 of 30 4.4 die placement dimensions and accuracy 200 2 all dimensions in mm figure 19. die placement figure 20. tolerances
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 26 of 30 4.5 cover glass 4.5.1 IBIS4-14000-M (monochrome) schott d-263 plain glass is the cover glass of the ibis4-14000 (monochrome). 4.5.2 ibis4-14000-c (color) s8612 glass is the cover glass of the ibis4-14000-c (color) specification ? ar coating: 400?690 nm r < 1.5% ? dig, haze, scratch 20 m after coating ? substrate: schott s8612 glass ? thickness: 0.7 mm 0.050 mm ? size: 31.9 x 44.9 mm 2 0.2 mm 0 10 20 30 40 50 60 70 80 90 100 400 500 600 700 800 900 wavelength [nm] transmission [%] figure 21. d-263 transmittance curve 0 10 20 30 40 50 60 70 80 90 100 400 500 600 700 800 900 1000 wavelength [nm] transmittance [%] figure 22. s8612 transmittance curve (w/o ar coating)
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 27 of 30 defects (digs, scratches) detected at final test using f/11 light source. glass defects that do not generate non-correctable pixels are accepted. 5.0 storage and handling 5.1 storage conditions note: rh = relative humidity 5.2 handling precautions special care should be taken when soldering image sensors with color filter arrays (rgb color filters), onto a circuit board, since color filters are sensitive to high temperatures. prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. the following recommendations are made to ensure that sensor perfor- mance is not compromised during end-users? assembly processes. 5.3 esd though not as sensitive as ccd sensors, the ibis4-14000 is vulnerable to esd like other standard cmos devices. device placement onto boards should be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machine model devices. take into account standard esd procedures when manipulating the device: ? assembly operators should always wear all designated and approved grounding equipment; grounded wrist straps at esd protected workstations are recommended including the use of ionized blowers. all tools should be esd protected. to ground the hum an body, provide a resistance of 1 mohm between the human body and the ground to be on the safe side. ? when directly handling the devi ce with the fingers, hold the part without the leads and do not touch any lead. ? to avoid generating static electricity: ? do not scrub the glass surface with cloth or plastic ? do not attach any tape or labels ? do not clean the glass surface with dust-cleaning tape ? when storing or transporting the device, put it in a container of conductive material 5.4 dust and contamination dust or contamination of the glass surface could deteriorate the output charac teristics or cause a scar. in order to minimize dust or contamination on the glass surface, take the following precautions: ? handle the device in a clean environment such as a cleaned booth (the cleanliness should be, if possible, class 100). ? do not touch the glass surface with the fingers. ? use gloves to manipulate the device 5.5 soldering soldering should be manually performed with 5 seconds at 350c maximum at the tip of the soldering iron. 5.6 precautions and cleaning avoid spilling solder flux on the cover glass; bare glass and particularly glass with antirefle ction filters may be adversely affected by the flux. avoid mechanical or particulate damage to the cover glass. avoid mechanical stress when mounting the device. 5.7 rohs (lead-free) compliance this paragraph reports the use of hazardous chemical substances as required by t he rohs directive (excluding packing material). description minimum maximum unit conditions temperature ?10 66 c @ 15% rh temperature ?10 38 c @ 86% rh table 14. chemical substances and info rmation about any intentional content chemical substance any intentional content? if there is any intentional content, in which portion is it contained? lead no - cadmium no - mercury no - hexavalent chromium no - pbb (polybrominated biphenyls) no - pbde (polybrominated diphenyl ethers) no -
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 28 of 30 information on lead free soldering IBIS4-14000-M: the product was tested successfully for lead-free soldering processes, using a reflow temperature profile with maximum 260c, minimum 40s at 255c and minimum 90s at 217c. ibis4-14000-c: the product will not withstand a lead-free soldering process. maximum allowed reflow or wave soldering temperature is 220c. hand so ldering is recommended for this part type. note: ?intentional content? is defined as any material demanding special attention is contain ed into the inquired product by following cases: 1. a case that the above material is added as a chemical com- position into the inquired product intentionally in order to produce and maintain the required performance and func- tion of the intended product . 2. a case that the above material, which is used intentionally in the manufacturing process, is contained in or adhered to the inquired product the following case is not trea ted as ?intentional content?: 1. a case that the above material is contained as an impurity into raw materials or parts of the intended product. the im- purity is defined as a subs tance that cannot be removed industrially, or it is produced at a process such as chemical composing or reaction and it cannot be removed technical- ly.
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 29 of 30 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 6.0 ordering information 6.1 part numbers 6.2 evaluation kit for evaluating purposes an ibis4-14000 evaluation kit is available. the ibis4-14000 eval uation kit consists of a multi- functional digital board (memo ry, sequencer and ieee 1394 fire wire interface) and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images from the sensor. all acquired images can be stored in different file formats (8 or 16-bit). all settings can be adjusted on the fly to evaluate the sensors? specs. default register values can be loaded to start the software in a desired state. please contact us for more information. table 15. ordering information part number package monochrome/color glass lid IBIS4-14000-M 49-pin pga package monochrome monochrome cyii4sm014kaa-gbc (preliminary) 49-pin pga package monochrome monochrome ibis4-14000-c 49-pin pga package rgb color color cyii4sc014kaa-gac (preliminary) 49-pin pga package rgb color color
IBIS4-14000-M ibis4-14000-c document #: 38-05709 rev. *a page 30 of 30 document history page document title: IBIS4-14000-M 14-megapixel cmos image sensor document number: 38-05709 rev. ecn no. issue date orig. of change description of change ** 310213 see ecn sil initial cypress release *a 428177 see ecn fvk layout converted figure 12 page 15 updated storage and handling section added ibis4-14000-c added

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